Skip to content

CPU SRAM Design Engineer – CPU Engineering
Company | Qualcomm |
---|
Location | Austin, TX, USA |
---|
Salary | $179000 – $268400 |
---|
Type | Full-Time |
---|
Degrees | Bachelor’s, Master’s |
---|
Experience Level | Senior, Expert or higher |
---|
Requirements
- BA/BS degree in Electrical Engineering with 12+ years of practical experience
- Experience with designing SRAM circuits
- Experience in industry standard custom design tools and flows
- Experience with circuit simulation and monte carlo analysis
- Experience with static timing analysis
Responsibilities
- Develop custom digital circuits for high-speed and low-power SRAM designs
- Schematic capture
- Layout planning and supervision
- Functional verification
- Simulation and margin verification
- Timing characterization
- Performing analysis steps necessary to generate all deliverable collateral models
- Interacting with CAD team to ensure proper and efficient model generation
- Interacting with Physical Design team resolve memory PPA challenges
- Depending on skill set, aid the team with contributions to modeling, DFT and/or analysis flow development.
Preferred Qualifications
- MS degree in Electrical Engineering; 10+ years of practical experience
- Strong knowledge of SRAM and Register File techniques with advanced custom circuit implementations
- Strong knowledge of high-performance and low-power design features and techniques
- Strong knowledge of semiconductor device fundamentals
- Familiar with variation-aware simulation in FinFet and Nanosheet technology nodes
- Experience with custom memory layout designs
- Experience with all memory analysis steps including design entry, functional verification, layout guidance, simulation, timing, power and electrical characterization.
- Good understanding of physical implementation impact on circuit performance
- Proficiency with the following tools: NanoTime, Ansys EMIR analysis, ESP-CV, Liberate power analysis
- Experience with memory logical models (Verilog) and functional verification.
- Experience with BIST and other DFT features.
- Experience with memory analysis flow development and planning.