CPU RTL Design Engineer

CPU RTL Design Engineer

Requirements

• Bachelors in Computer Engineering or Electrical Engineering with 6+ years of experience
• OR Masters degree in Computer Engineering or Electrical Engineering with 4+ years of experience
• Experience in high-performance, lower-power CPU design
• Experience in Cache/Memory subsystem design and computer architecture, RTL Verilog, V2K, or System Verilog with a working knowledge of hardware modeling issues and logic design and debug skills, Timing convergence
• Proficient with static timing analysis, UPF and lint checks
• Experience in Scripting in an interpreted language (e.g. TCL, Perl, Python, Ruby)

Responsibilities

• Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs
• Participates actively in the definition of architecture and microarchitecture features of the CPU being designed
• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation
• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features
• Documents micro architectural specs (MAS) of the CPU features being designed
• Supports SoC customers to ensure high quality integration of the CPU block

Preferred Qualifications

• Experience in Modern energy-efficient/low-power logic design techniques, including those specifically applicable to high frequency optimization
• Knowledge of Intel Architecture ISA and system architecture, including x86 assembly language
• Experience with high speed circuit design and optimization for data path, circuits and/or arrays
• Knowledge of circuit planning and timing convergence
• Knowledge with x86 memory management