CPU Implementation Engineer
| Company | Apple |
|---|---|
| Location | Beaverton, OR, USA |
| Salary | $Not Provided – $Not Provided |
| Type | Full-Time |
| Degrees | Bachelor’s |
| Experience Level | Expert or higher |
Requirements
- Minimum BS and 10+ years of relevant industry experience
- Experience in logic design and digital circuits
- Experience with low power and high frequency design techniques
- Experience in TCL or Perl
Responsibilities
- Work with micro-architects to help define the micro-architecture and assist with design feasibility and power, performance, and area (PPA) trade-offs
- Drive RTL-to-GDS design convergence through microarchitecture and logic (RTL) optimizations using synthesis and place-and-route tools targeting ambitious goals for PPA
- Responsible for block-level design delivery along with closure of backend flows, electrical requirements, and improving silicon yield
- Work closely with internal CAD and PD methodology teams on industry standard synthesis/PNR tool features and optimizations and their adoption in CPU design
- Work with x-functional top-level teams on the aspects of CPU floorplan, timing, power, reliability, and testability
- Work closely with custom IP teams to define and co-optimize memory macros, library standard cells to improve design PPA
Preferred Qualifications
- Familiarity with high performance CPU microprocessor architecture and memory sub-system
- Knowledge in deep sub-micron technology along with its implications to timing, power, and area
- Must have proficiency in using industry standard logic Synthesis, PnR, STA and Power analysis tools along with floor-planning, physical design partitioning, and timing budgeting, to converge complex designs
- Excellent communication and interpersonal skills
- Ability to work independently and/or lead a physical design partition in collaboration with x-functional teams