ASIC Timing and Methodology Engineer – ASICS Engineering
| Company | Qualcomm |
|---|---|
| Location | San Diego, CA, USA |
| Salary | $Not Provided – $Not Provided |
| Type | Full-Time |
| Degrees | |
| Experience Level | Mid Level |
Requirements
- Good programming skills in Python, Perl, TCL, Unix shell, C/C++
- Understanding of intricate timing paths (digital, analog, mixed signal)
- Good understanding of RTL to GDS digital flow
- Execution knowledge
- Experience with Spice simulations (Hspice/Finesim/AFS/Spectre/Infinisim) for PVT corners validation and STA vs spice correlation
- Knowledge of DC/DCT/DCG/Genus/Oasis, ICC2/Fusion/Innovus/Aprisa, RedHawk/SeaHawk/Voltus
Responsibilities
- Work with physical design team and other teams on timing closure, CAD teams, IP teams, and Design Technology Teams for flow scripts/tools development and validation
- Facilitate and drive STA methodology for Qualcomm using PT-SI, Tempus, and best in class timing ECO tools
- Work on timing sign off specification for different projects and support timing sign off for complex SOC’s
- Hands-on contribution for STA timing sign off
- Improve timing convergence process across the company, design PPA, yield, and support new advanced process technologies bring-up from PDK to VLSI design production
Preferred Qualifications
- ML modeling experience is a plus