ASIC Engineer – Formal Verification
| Company | Meta |
|---|---|
| Location | Austin, TX, USA, Remote in USA, Sunnyvale, CA, USA |
| Salary | $173000 – $249000 |
| Type | Full-Time |
| Degrees | Bachelor’s |
| Experience Level | Senior |
Requirements
- Bachelor’s degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
- 5+ years of experience in Formal Verification
- Experience with Formal Verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc
- Proven understanding of Formal Verification methodologies, complexity reduction techniques and abstraction techniques
- Proven analytical skills to craft novel solutions to tackle industry-level complex designs
- Demonstrated experience with effective collaboration with cross functional teams
- Fluency in hardware description languages, such as SystemVerilog and SVA
- Proficiency in scripting languages such as Python, Perl, or Tcl
- Experience with JasperGold or VC-Formal
Responsibilities
- Provide technical leadership in Formal Verification
- Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level
- Work with Architecture and Design team to come up with Formal driven specification and implementation
- Define formal verification scope, create formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level
- Build reusable/scalable environments for Formal Verification and deploying the tools
- Evaluate and recommend EDA solutions for Formal Verification
- Provide training for internal teams and mentoring engineers related to Formal Verification Technology
Preferred Qualifications
- Experience to quickly understand and interpret specifications and extract design behaviors/properties
- Experience in formal property verification of complex compute blocks such as DSP, CPU, GPU or HW accelerators
- Experience with complex SoCs
- Formal verification experience in clock domain crossing, IP-XACT based register verification and low power
- Experience with development of fully automated flows from specification to fully verified designs
- Experience with simulators and waveform debugging tools