ASIC Engineer – Design
| Company | Meta |
|---|---|
| Location | Austin, TX, USA, Sunnyvale, CA, USA |
| Salary | $173000 – $249000 |
| Type | Full-Time |
| Degrees | Bachelor’s, Master’s, PhD |
| Experience Level | Senior, Expert or higher |
Requirements
- Bachelor’s degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 8+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration
- RTL development using Verilog, System Verilog and HLS
Responsibilities
- Architecture exploration
- Micro-architecture development
- Soft and hard IP identification, selection and integration. Collaboration with verification and emulation teams in test plan development and debug
- Collaboration with implementation team to close the design on timing and power
Preferred Qualifications
- Experience in data path development
- Experience in CPU, NOC, Memory and Peripheral Subsystems
- Experience with Synthesis, Timing Closure and Formal Verification Methodology
- Master’s or PhD degree in Electrical Engineering, Computer Science or related areas