Senior Design Verification

Deep knowledge of SystemVerilog and UVM testbenches.
10+ years of Design Verification experience.
Experience in verification of memory controllers is a plus.
Experience developing scalable and portable testbenches and components.
Experience working on block and full chip verification.
Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, gate level simulations.
Proficient in scripting languages such as Python.
Good interpersonal skills and the ability and desire to work as a standout colleague are a must.
Extremely self-motivated and eager to solve problems.

Own and drive the end-to-end verification of a critical IP block from early planning to post-silicon validation for high-performance AI/ML chip.
Define and implement verification strategy, test plans, coverage metrics, and methodologies tailored for memory controller verification.
Develop and maintain constrained-random and directed testbenches using industry-standard methodologies (e.g., UVM).
Collaborate with cross-functional teams, including architecture, RTL design, physical design, firmware, and validation.
Analyze and debug complex issues across simulation, emulation, and silicon bring-up phases.
Continuously enhances verification infrastructure and flows to improve efficiency and quality.
Review design and architecture specifications to ensure functional correctness and testability.
Mentor and guide junior team members on technical issues and professional development.
Provide regular updates and strategic input to leadership on progress, risks, methodology, and resourcing needs.
Contribute to the evolution of the overall verification methodology and best practices across the organization.