GPU Logic Design Engineer

GPU Logic Design Engineer

Requirements

• Strong technical and communication skills
• Experience in designing and/or integrating IP for discrete graphics SoC
• Ability to create designs that improve product KPIs
• Experience with SoC Architecture and platform architecture teams
• Knowledge of design trade-offs balancing risk, area, power, performance, validation complexity, and schedule
• Ability to create micro architectural specification documents
• Experience working with external vendors on tools or IPs
• Ability to drive vendor’s methodology to meet silicon design standards
• Experience in architecting area and power efficient low latency designs
• Proficiency in power and area efficient RTL logic design and DV support
• Experience running tools to ensure lint-free and CDC/RDC clean design
• Knowledge of synthesis and timing constraints
• Experience achieving multiple tape-outs reaching production with first pass silicon
• Hands-on experience with FPGA emulation, silicon bring-up, characterization, and debug
• Ability to work with multi-functional teams across geographical boundaries
• Strong verbal and written communication skills
• Good understanding of Verilog and System Verilog, synthesizable RTL
• Knowledge of modern design techniques and energy-efficient/low power logic design
• Familiarity with power estimation, modeling, profiling, and post silicon power correlation
• Background in computer architecture
• Knowledge of bus fabric including APB/AHB/AXI
• Experience with power management with multiple power domains, UPF, and power state tables
• Knowledge of lint tools, CDC and RDC tools, timing constraints, and fishtail
• Knowledge of connectivity tools
• Understanding of key SoC design elements, arbiters, async FIFOs, DMAs, and basic Controllers
• Comprehension of asynchronous clock crossing means and methodologies
• Proven track record of bringing logic designs into high volume production
• Ability to work well in a team and be productive under ambitious schedules
• Self-motivated and well organized

Responsibilities

• Designing and/or integrating IP for a discrete graphics SoC
• Creating a design to produce key assets that help improve product KPIs for discrete graphics products
• Working with SoC Architecture and platform architecture teams to establish silicon requirements
• Making appropriate design trade-offs balancing risk, area, power, performance, validation complexity, and schedule
• Creating micro architectural specification documents for the design
• Working with external vendors on tools or IPs required for the development of micro-architecture, design, and design qualification of custom silicon designs
• Driving vendor’s methodology to meet world-class silicon design standards
• Architecting area and power efficient low latency designs with scalability and flexibility
• Performing power and area efficient RTL logic design and DV support
• Running tools to ensure lint-free and CDC/RDC clean design, VCLP
• Managing synthesis and timing constraints
• Achieving multiple tape-outs reaching production with first pass silicon
• Driving and improving digital design methodology to achieve high quality first silicon
• Collaborating with multi-functional teams within Intel and external vendors to resolve architectural and implementation challenges

Preferred Qualifications

No preferred qualifications provided.