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ASIC Engineer – Design Verification
| Company | Meta |
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| Location | Sunnyvale, CA, USA |
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| Salary | $178763 – $192170 |
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| Type | Full-Time |
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| Degrees | Bachelor’s |
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| Experience Level | Mid Level |
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Requirements
- Requires a Bachelor’s degree (or foreign degree equivalent) in Electrical Engineering, Computer Science, Engineering, Information Systems, Analytics, Mathematics, Physics, Applied Sciences, Business Administration (MBA) or a related field and 3 years of experience in the job offered or in a computer-related occupation.
- Experience must include 3 years of experience in the following:
- 1. Experience in SystemVerilog/UVM methodology or C/C++ based verification.
- 2. Track record of ‘first-pass success’ in ASIC development cycles.
- 3. Experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies.
- 4. Experience in EDA tools and scripting (Python, TCL, Perl, or Shell) used to build tools and flows for verification environments.
- 5. Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle.
Responsibilities
- Define and implement block/IP/SoC verification plans, build verification test benches to enable block/IP/sub-system/SoC level verification.
- Develop functional tests based on verification test plan.
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage.
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team.
- Collaborate with cross functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality.
Preferred Qualifications
No preferred qualifications provided.
