DDR PHY Timing Design Engineer – ASICS Engineering

DDR PHY Timing Design Engineer – ASICS Engineering

Requirements

• 2+ years industry experience with static timing analysis (STA) and PrimeTime constraints development.
• Unix/Perl/TCL scripting (must be comfortable with writing scripts)
• Excellent communication skills and ability to work across multiple teams across global locations.

Responsibilities

• Focused analysis and ownership of specific DDR PHY architecture components for timing closure bottlenecks and convergence feasibility.
• Identification and analysis of timing bottlenecks and mitigation solutions.
• Guidance to front-end and physical teams on all aspects of timing considerations.
• Development and support of PrimeTime STA timing constraints.
• Development of scripted automation for efficient data processing.

Preferred Qualifications

• Experience in DDR interface operation and off-chip timing considerations, including signal/power integrity (LPDDRx, DDRx, HBM).
• Good understanding of architecture, system, and integration aspects for DDR PHYs.
• Good understanding of design for yield and production challenges with DDR systems.