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ASIC Engineer – Design Verification
| Company | Meta |
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| Location | Menlo Park, CA, USA |
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| Salary | $238228 – $287650 |
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| Type | Full-Time |
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| Degrees | Bachelor’s |
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| Experience Level | Mid Level |
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Requirements
- Requires a Bachelor’s degree (or foreign equivalent) in Computer Science, Electronics Engineering, or related field or a related field and three years of work experience in the job offered or in an engineering-related occupation
- Requires three years of experience in the following: 1. System Verilog / UVM 2. Constraint Random Testbench 3. IP/SoC (System On Chip) Verification 4. Debugging design 5. Functional Coverage 6. Automation Scripting 7. Regression management, AND 8. Verification IP
Responsibilities
- Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification and develop functional tests based on verification test plan
- Collaborate with cross-functional teams like Design, Model, Emulation, and Silicon validation teams towards ensuring the highest design quality
- Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools, and technologies from the industry
- Telecommute from anywhere in the U.S. permitted.
Preferred Qualifications
No preferred qualifications provided.
