Silicon Verification Manager – AI Accelerators

Silicon Verification Manager – AI Accelerators

Requirements

• 4+ years supporting design verification teams, driving strategy/planning and cross-functional partner collaboration on low power/high performance IP/SOC projects
• 2+ years of Management or Technical leadership experience
• 6+ years of System Verilog UVM DV experience
• Knowledge with assertions (SVA) or others
• Knowledge of digital ASIC design flows, project management and milestones
• Knowledge of X-propagation, UPF-power aware, Gate-level simulations
• Experience with at least 1 procedural programming language (C, C++, Python etc)
• Results oriented, self-motivated, proactive with demonstrated critical thinking
• MS EE/CS or equivalent experience

Responsibilities

• Support design verification team members’ skills development, career and personal growth, task prioritization and ownership
• Work with cross-functional partner teams defining and improving SW-HW verification methodologies and strategies for Machine learning accelerator IP
• Define and track project milestones and detailed plans for module- and top-level functional, power, and performance verification
• Support implementation of scalable test benches including checkers, reference models, and assertions, directed and random tests
• Track and report functional coverage metrics, power and performance metrics, and bugs encountered and fixed
• Support SW-HW co-design, development of SW unit tests and/or custom kernels
• Support post silicon bring-up and debug activities

Preferred Qualifications

• Experience in Machine Learning IPs Silicon development
• Exposure to other verification methodologies (formal, co-simulation, etc)
• FPGA/Emulation prototyping and debug experience
• Experience with SW-HW co-design, firmware/HW interaction testing
• Experience with AI algorithms, DSP coding and optimization
• Experience to collaborate and/or lead in a team environment
• PhD in Electrical Engineering or Computer Science or equivalent experience