Senior ASIC Design Engineer - Dfx

Senior ASIC Design Engineer – Dfx

Master’s Degree or equivalent experience in Electrical Engineering
5+ years of meaningful experience in SOC architecture and design experience
Experience in micro-architecture and RTL development (Verilog)
Verification experience using UVM is a plus
Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate designs using vendor tools
Good exposure to cross functional areas including RTL & clocks design, STA, place-n-route and power
Experience in Silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development
Strong programming and scripting skills in Perl, Python or Tcl desired
Exceptional written and oral interpersonal skills with the curiosity to work on rare challenges

Responsible for the architecture, design, implementation and verification of fuse controller and other DFT IPs for our next generation products
Build architectural trade-offs based on features, performance requirements and system limitations
Comfortable working with RTL and debugging tools
Work with other architects, platform and software teams to define feature set for future designs
Collaborate and coordinate with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams
Work on generating test plans and verification infrastructure and tests
Support functional and DFT full chip level verification efforts
Support post-silicon bring up and validation activities
Help mentor junior engineers on test designs and trade-offs including cost and quality