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Silicon Validation Engineer
| Company | NVIDIA |
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| Location | Santa Clara, CA, USA |
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| Salary | $168000 – $310500 |
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| Type | Full-Time |
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| Degrees | Bachelor’s, Master’s |
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| Experience Level | Expert or higher |
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Requirements
- BS or MS degree in EE/CE or equivalent experience
- Effective in a collaborative environment
- 8+ years of experience in developing end-to-end silicon validation and stress testing, PVT methodologies for next-generation silicon
- Deep understanding of GPU/SOC system-level architecture
- Working experience with silicon active and low power features, boot, binning, PVT sensitivity, platform component losses
- Post silicon debug and evaluate fix options against product needs
- Effective collaboration and communication across different functional teams.
Responsibilities
- Develop new end-to-end methodologies, processes, and workflows targeting system-level silicon stress, concurrency, and PVT coverage.
- Lead debug efforts from the HW side to root cause feature sequences bugs, silicon bugs, and sophisticated system-level issues caused by interactions between multiple HW and SW features.
- Bringup new flows, tests, and PVT solutions.
- Apply insights from bring-up execution and post-action reviews to continually improve coverage.
Preferred Qualifications
No preferred qualifications provided.
