Principal Physical Design and Timing Lead

Principal Physical Design and Timing Lead

Requirements

• Bachelor’s degree in Computer Science, Electrical Engineering, or related fields with 10-15 years of professional experience, or Master’s/PhD with 5-10 years of experience.
• 3 years of practical experience in physical design at all levels of hierarchy with multiple ASICs/SOCs.
• Physical design knowledge and experience, from netlist handoff to GDS tape-out.
• Extensive experience with floorplanning at a sub-system/partition level, considering boundary snap of power/technology and pin assignment.
• Proficient in running sub-system/partition level signoff, including physical verification (DRC and LVS), along with power integrity (EMIR).
• Experienced in leading a small team of block-level engineers, coordinating at the sub-system/partition level.
• Good knowledge of Verilog/VHDL, and a track record of collaboration with RTL team.
• Good understanding of digital logic and architecture.
• Proficient in UNIX and shell-based scripting.
• Knowledge and experience with TCL language.
• Diligent, detail-oriented, and able to handle assignments with minimal supervision.
• Must possess good communication skills, be a self-driven individual, and a good team player.

Responsibilities

• Lead a large complex sub-system/partition through all phases of the design.
• Be responsible for floorplanning a sub-system/partition, pushing down block boundary and pin assignment to team members.
• Work with various teams to pull in their required portion of the sub-system, such as DFT and clock distribution teams.
• Lead a small group of engineers at the block level, ensuring they are progressing, meeting milestones on schedule and quality, and delivering correct outputs.
• Work closely with block-level PD engineers in debugging and resolving timing and routing issues across all hierarchical levels.
• Be an active team member on physical design methodology and flow development.
• Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes.
• Write scripts in Perl, Python, and TCL to extract data and achieve productivity enhancements through automation.

Preferred Qualifications

• 5 years of practical experience as a leader of a small team at the sub-system/partition level for multiple ASICs/SOCs.
• Experience working with timing and clock teams on planning and integration of high-speed clock distribution.
• 5nm/3nm experience with floor planning.
• Floor planning and Physical Design with Cadence Innovus.
• Physical Verification with Siemens Calibre.
• Power Integrity Signoff with Cadence Voltus.
• Peripheral IO Pad assignment and associated RDL.
• Bump assignment planning and collaboration with full-chip and package team.
• Experience with Analog IP integration and implementation.
• Knowledge and experience with Python language.
• Experience with low power design methodology and implementation.
• Have led or participated in Physical Design and Integration methodology and flow development.