Principal Physical Design and Integration Engineer

BS in EE/CE/CS with 10+ years of experience, or MS in EE/CE/CS with 5+ years of experience
5 years of practical experience in physical design at all levels of hierarchy with multiple ASICs/SOCs
Physical design knowledge and experience, from RTL or netlist handoff to GDS tape-out
Extensive experience with floorplanning at a sub-system/partition level, considering boundary snap of power/technology and pin assignment
Proficient in running chip/sub-system/partition level signoff, including physical verification (DRC and LVS), along with power integrity (EMIR)
Experienced in leading a team of block-level engineers, coordinating at the sub-system/partition level
Good knowledge of Verilog/VHDL, and track record of collaboration with RTL team
Good understanding of digital logic and architecture
Proficient in LINUX and shell-based scripting
Knowledge and experience with TCL language
Diligent, detail-oriented, and able to handle assignments with minimal supervision
Must possess good communication skills, be a self-driven individual, and a good team player

Be the leader on a large complex chip/sub-system/partition through all phases of the design
Responsible for floorplanning a chip/sub-system/partition, pushing down block boundary and pin assignment to team members
Work with a variety of teams to pull in their required portion of the sub-system, such as DFT and clock distribution teams
Leading a small group of engineers at the block level, ensuring they are progressing, meeting milestones on schedule and quality, and correct deliverables
Work closely with the block level PD engineers in debugging and resolving timing and routing issues across all hierarchical levels
Be an active team member on physical design methodology
Provide technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes
Write scripts in Perl, Python and TCL to extract data and achieve productivity enhancements through automation

BS in EE/CE/CS with 15+ years of experience, or MS in EE/CE/CS with 10+ years of experience
10 years of practical experience as a leader of a team at the chip/sub-system/partition level for multiple ASICs/SOCs
Worked with timing and clock teams on planning and integration of high-speed clock distribution
5nm/3nm experience with chip-level floorplanning, including bump/UBM, MIMCAP insertion, AP routing, and DFM planning
Floorplanning and Physical Design with Cadence Innovus
Physical Verification with Siemens Calibre and/or Synopsys ICV
Power Integrity Signoff with Cadence Voltus
Peripheral IO Pad assignment and associated RDL
Bump assignment planning and collaboration with fullchip and package team
Experience with Analog IP integration and implementation
Knowledge and experience with Python language
Experience with low-power design methodology and implementation
Have led or participated in Physical Design and Integration methodology