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Principal Engineer – Physical Design
| Company | Marvell |
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| Location | Santa Clara, CA, USA |
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| Salary | $205000 – $215000 |
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| Type | Full-Time |
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| Degrees | Bachelor’s |
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| Experience Level | Senior, Expert or higher |
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Requirements
- Bachelor’s or foreign equivalent degree in Electrical/Electronic Engineering, Computer Science/Engineering, or a related field
- Five (5) years of experience in the job offered or related occupation
- Five (5) years with physical design implementation of complex blocks from RTL to GDS/Oasis
- Five (5) years with advanced process nodes (5nm and 3nm)
- Five (5) years with Place and Route tools such as Innovus and ICC2
- Five (5) years with signoff physical verification, block level STA, and EMIR analysis
- Five (5) years with synthesis, physical design, and timing closure
- Five (5) years with floorplanning with emphasis on timing and routability convergence
- Five (5) years with clock tree synthesis and setup/hold timing considerations
- Five (5) years with dynamic and leakage power optimization strategies
- Five (5) years with TCL scripting
Responsibilities
- Perform complex custom Block Level Synthesis and block floorplan
- Work closely with full chip teams, Static Timing Analysis STA team, and block owners to develop Marvell Switch devices layout till Tape-out
- Own initial spec development, implementation, signoff, and delivery of blocks and components that go into our advanced switch products
- Build customized clock structure
- Own block level Place and Route implementation for multiple Switch BU blocks
- Work closely with physical verification, timing, and power network integrity signoff checks to ensure blocks meet rigorous QoR requirements
- Work with flow teams to develop and deploy updates for new projects and processes
Preferred Qualifications
No preferred qualifications provided.
