Senior Staff Engineer – Design Verification

Senior Staff Engineer – Design Verification

Requirements

• Master’s or foreign equivalent degree in Electrical/Electronic Engineering, Computer Science/Engineering, or a related field
• Three (3) years of experience in the job offered or related occupation
• Developing complex random verification environment using System Verilog/UVM
• Writing complex System Verilog Assertions & constraints
• Writing & Analyzing Functional coverage and closure
• Writing test plan and testcases using System Verilog/UVM
• Debugging and performing verification closure of block or sub-system
• Developing verification collaterals using programming language C/C++
• Scripting/Automation using Python or Perl

Responsibilities

• Develop comprehensive test plan and architect verification infrastructure for System-on-chip (SoC)
• Build Block & sub-system level SV/UVM test bench development from scratch
• Write constraint random test cases and directed test cases to achieve functional and code coverage goals
• Debug failures and work with designers & software team to resolve issues
• Develop functional verification of design on block, sub-system and SoC level
• Develop testcases and rate monitors to measure latency and performance
• Develop test automation framework using Python/Perl

Preferred Qualifications

No preferred qualifications provided.