Sr/Principal Engineer: FPGA/ASIC Engineer

Sr/Principal Engineer: FPGA/ASIC Engineer

Requirements

• 5 years of relevant professional experience with a Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering or other STEM (Science, Technology, Engineering or Mathematics) discipline; 3 years with Masters; 0 years with a PhD
• Must have hands on experience with VHDL within the past 3 years
• Well versed in VHDL design for an aerospace environment or space application
• Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place and route, static timing analysis, and power analysis
• US Citizen
• Must possess an active/current Top-Secret/SCI at time of application
• 9 years of relevant professional experience with a Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering or other STEM (Science, Technology, Engineering or Mathematics) discipline; 7 years with Masters; 4 years with a PhD
• Experience with VHDL design or Advanced /verification ​for FPGA’s
• Experience with translating system requirements into programmable logic requirements, design documents, and test specifications
• Proven experience defining architectures or team leadership

Responsibilities

• Research
• Requirements analysis
• Systems architecture
• Design
• Coding
• Test bench design
• Verification
• Synthesis
• Place & route for Command and Data Handling (CD&H) products

Preferred Qualifications

• Experience with DSP, MATLAB, and SimuLink
• Experience with VHDL design for Software Defined Radios
• Experience with Xilinx and Microchip (RTG4) devices
• Experience with Electronic Design Automation (EDA) Tools: Vivado, Quartus, QuestaSim
• Knowledgeable in FPGA physical constraints and achieving timing closure
• Experience with board or system level debug using test equipment such as oscilloscopes and logic analyzers
• Generation of Test Benches and support of formal VHDL Verification