Senior Engineer - Analog Design Engineering

Senior Engineer – Analog Design Engineering

Must have a Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering or a related field (willing to accept a foreign education equivalent) and 3 years of experience as an Electronics Engineer or related occupation designing, reviewing, implementing, and documenting test plans.
Demonstrated Expertise (DE) designing system and controller architectures, and performing Transistor level design for BJT/CMOS devices involving high voltage and low voltage BUCK, BOOST, BUCK-BOOST and isolated DC-DC converters including designing analog building blocks;
DE simulating and analyzing for DC/transient/frequency responses, gain and output resistance, transconductance (gm), common-mode rejection ratio (“CMRR”)/power supply rejection ratio (“PSRR”), and dominant pole compensation;
DE performing schematic design using Cadence Integrated Circuit Front to Back (“ICFB”), circuit simulation, component selection, placement, matching and basic DRC checks for layouts, post-layout extraction simulation techniques, and hardware implementation;
DE evaluating circuits using lab equipment such as spectrum analyzers, oscilloscopes, signal generators, current probes, electronic loads, power supplies and multimeters; and
DE conducting validation tests such as electrical stress and de-rating, worse case conditions, no load test, reliability prediction, thermal test, failure mode effect analysis, and loss estimations.

Design high performance DC-to-DC converters with companion mixed-signal ICs targeted at industrial power management markets.
Design and simulate transistor-level circuits for Bipolar Junction Transistor (“BJT”)/Complementary Metal Oxide Semiconductor (“CMOS”) devices.
Architect, implement, and analyze trade-offs of analog blocks.
Responsible for verification of circuit (IC) performance using Cadence tools.
Perform AMS/System Verilog simulations for mixed signal verification.
Evaluate and troubleshoot complex integrated circuit problems in the laboratory.
Interface with test, product, and applications engineering to successfully bring new products from initial concept through production release.
Supervise layout engineers to implement IC’s using layout techniques to account for IR drop, RC delay, electromigration, self-heating, coupling capacitance, Shallowtrench Isolation (“STI”)/Well Proximity Effect (“WPE”)/Latch Up (“LU”)/Electro-Static discharge (“ESD”)/Safe Operating Area (“SOA”).
Author and review product datasheets.
Collaborate with layout engineers to oversee mask design, including the components placement, components connection, and top-level arrangement.
Conduct further experiments and simulations to rectify discrepancies or defects identified once parts return from fabrication.

No preferred qualifications provided.