SoC RTL Security Design Engineer

SoC RTL Security Design Engineer

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 3 years of experience with RTL coding using Verilog/SystemVerilog.
• Experience with industry-standard EDA tools for simulation, synthesis and power analysis.

Responsibilities

• Create and review the security subsystem’s design microarchitecture specifications.
• Develop SystemVerilog RTL to implement logic for ASIC products according to established coding and quality guidelines.
• Work with architecture and power teams to evaluate security features and their impact.
• Work with design validation (DV) teams to create test plans to verify and debug RTL designs.
• Work with physical design teams to ensure design meets physical requirements and timing closure.

Preferred Qualifications

• Master’s degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 5 years of experience in ASIC design with 3 years of experience working on security design.
• Experience interacting with software, system hardware, and other cross-functional teams.
• Experience developing and integrating security IPs into an SoC.
• Experience with scripting languages (e.g., Tcl, Python or Perl).
• Understanding of digital design fundamentals, including synchronous and asynchronous logic, state machines and bus protocols.