ASIC and/or FPGA Design & Verification Engineer – Lead – Senior or Principal

ASIC and/or FPGA Design & Verification Engineer – Lead – Senior or Principal

Requirements

• Bachelor of Science degree from an accredited course of study in engineering, engineering technology (includes manufacturing engineering technology), chemistry, physics, mathematics, data science, or computer science
• 5+ years of ASIC/FPGA design or verification experience
• Experience with ASIC/FPGA architectural definition, and detailed design implementation and functional verification using SystemVerilog with delivery/release of production designs
• Professional experience with hardware-based integration and test of ASIC/FPGA designs
• Proven record of leading ASIC/FPGA design and/or verification teams, including tracking and reporting progress to stakeholders

Responsibilities

• Lead FPGA/ASIC designs, including multi-FPGA/ASIC programs and teams with design and verification engineers, and manage team execution to meet program milestones
• Collaborate with customers, system engineers, and hardware engineers to drive requirements capture and architect digital logic functions to meet mission/customer needs
• Explore trade-space of potential ASIC/FPGA technologies and determine the optimal parts, weighing Schedule, Cost, Risk, Area, Power (SCRAP) vs. performance
• Implement FPGA/ASIC with latest design practices and tools from block-level micro-architecture, through HDL coding, and physical design realization (through gate-level netlists for ASIC designs)
• Integrate DSP IP from Boeing’s algorithm team and third-party IP as needed
• Perform static timing analysis, LEC, CDC, linting, and other necessary checks to ensure the design is completed on schedule
• Develop Functional Coverage Models and perform Code Coverage to verify designs in simulation
• Create self-checking and reusable test benches from scratch, applying Object Oriented Programming concepts such as Inheritance and Polymorphism, and leverage UVM to create drivers, monitors, predictors, and scoreboards
• Drive FPGA-based prototyping and validation depending on program and system requirements and complexity
• Validate design through hardware integration test with special test equipment, test-beds, and higher-level systems as needed
• Train and mentor less senior engineers across the department and help build effective project teams

Preferred Qualifications

• 10+ years of related work experience or an equivalent combination of education and experience
• Master’s Degree in EE, Computer Engineering/Science, or related field, or equivalent experience
• Experience with hardware emulators, especially Palladium
• Proficiency with hardware verification languages: System Verilog, System Verilog Assertions
• Ability to executable test plans
• Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc.
• Ability to create self-checking and reusable testbenches from scratch
• Experience developing Functional Coverage Models and Closing Code Coverage
• Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet)
• Proficient in scripting languages: Make, Perl, Python, etc.
• Revision Control Systems: svn, cvs, git
• Proficient in Linux Environments
• Familiarity with space-based design techniques and radiation mitigation
• Demonstrated history of 1st pass success with ASIC designs