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ASIC Design Senior Manager
| Company | Broadcom Limited |
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| Location | Fort Collins, CO, USA |
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| Salary | $146000 – $234000 |
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| Type | Full-Time |
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| Degrees | Bachelor’s, Master’s |
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| Experience Level | Expert or higher |
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Requirements
- Minimum of 15 years of overall experience of which a minimum of 5 years is in management.
- Candidate must have the legal right to work in the US.
- Good communication & teamwork skills
- Strong leadership skills
Responsibilities
- Lead & manage a leading-edge ASIC design team responsible for all aspects of physical ASIC design
- Customer communication & management
- Internal communication to align and drive schedules with IP teams, DFT teams, packaging teams, quality teams, etc.
- Ensure on-time execution and first-time right silicon for all ASIC design programs
- Lead, manage, track and report each of the following chip design tasks: Floor planning chips and blocks, Top & Block-Level Routing, Timing, both mission mode and test modes, Integration of memories, SerDes, and I/O, Work effectively with cross functional teams, Integration of test and clocking structures, Design of complex standard cell and custom blocks, Physical verification to ensure error free artwork/mask release.
- Understanding of design tradeoffs for power, area, and speed.
- Understanding of complex issues related to timing closure, power integrity and signal integrity.
- Ability to debug complex design issues both during and after release.
Preferred Qualifications
- Bachelor’s in Electrical Engineering, Computer Engineering, or Computer Science or Master’s Degree
- Management or technical leadership experience (5-10 years)
- Electrical Engineering background: CMOS digital and/or analog circuit basics
- Program Management skills – working knowledge of making appropriate tradeoffs between scope, schedule and resources to manage very complex programs from cradle to grave
- Proficiency in: CAD/EDA familiarity or experience (in one or more areas), Design For Test concepts, tools, Custom circuit or ASIC design tools and flows, Static timing analysis concepts, tools, Industry circuit data formats (e.g. SPICE, LEF/DEF, Verilog, OpenAccess, GDS/OASIS)
