Principal CPU Systems Debug Architecture/RTL Engineer - CPU Engineering

Principal CPU Systems Debug Architecture/RTL Engineer – CPU Engineering

MS degree in Computer or Electrical Engineering with 15+ years of CPU RTL or similar experience.
Thorough knowledge of microprocessor architecture including expertise in CPU System Debug, Micro-architecture Debug techniques, Scan dump and mem-dump architectures, and understanding of Design for test and Design for Debug architecture.
Knowledge of Verilog and/or VHDL. Experience with simulators and waveform debugging tools.
Knowledge of logic design principles along with timing and power implications.

Performance exploration and power optimization opportunities. Explore high performance strategies working with the CPU modeling team.
Work together with Post-silicon team to enhance debug features to reduce time to debug.
Microarchitecture development and specification. From early high-level architectural exploration, through micro architectural research and arriving at a detailed specification.
RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing goals.
Functional verification support. Help the design verification team execute on the functional verification strategy.
Performance verification support. Help verify that the RTL design meets the performance goals.
Design delivery. Work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability and power.
Work alongside with Software, Firmware and platform team to make CPU systems features enabled in the products.

MS degree or PhD in Computer or Electrical Engineering.
Work hand in hand with SoC and CPU architects to close on Debug requirements and enhancements.
Understanding of low power microarchitecture techniques.
Understanding high-performance techniques and trade-offs in CPU microarchitecture.
Experience using a scripting language such as Perl or Python.