Posted in

Server High Performance Compute Subsystem Lead – CPU Engineering

Server High Performance Compute Subsystem Lead – CPU Engineering

CompanyQualcomm
LocationSanta Clara, CA, USA
Salary$Not Provided – $Not Provided
TypeFull-Time
DegreesBachelor’s, Master’s
Experience LevelExpert or higher

Requirements

  • Bachelor’s degree in Computer Science/Engineering, Electrical Engineering, or a related field.
  • Over 10 years of experience in designing a high-performance compute subsystem for CPU, GPU, NPU, etc.
  • Experience in micro-architecture and/or design of one or more functional blocks of a CPU/SoC like L2/L3, directory, interconnects, etc.
  • Strong expertise in power management of a high-performance system including management of active power, idle low power and silicon/system limits
  • Strong expertise in defining and developing debug features associated with high performance designs
  • Strong technical documentation skills, along with excellent written and verbal communication abilities.

Responsibilities

  • Take on a leadership role in developing the micro-architecture and design of high-performance CPU subsystem
  • Develop High-Level Architecture and Micro-Architecture specifications that can translate to RTL design.
  • Deliver successful RTL design in collaboration with Design Verification and Physical Design teams.
  • Prepare and present clear and comprehensive technical documentation to meet the needs of stakeholders, including engineering teams, senior management and internal partners.

Preferred Qualifications

  • Master’s in Computer Science/Engineering, Electrical Engineering, or related field.
  • 15+ years in CPU and/or SoC Design.
  • Expertise in the design of multi-GHz processors with focus on critical path optimization
  • Experience with ARM ISA and AMBA protocols including CHI
  • Experience in design of coherent interconnects is a plus
  • Proven track record in hyperscale data center solutions.
  • Strong understanding DFx technologies like DFT, DFY, DFM
  • Expertise with developing RAS features